SH7280 Datasheet, PDF (1106/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 22 Controller Area Network (RCAN-ET) (SH7286 Only)
22.7 DMAC Interface
The DMAC can be activated by the reception of a message in RCAN-ET mailbox 0. When
DMAC transfer ends after DMAC activation has been set, flags of RXPR0 and RFPR0 are cleared
automatically. An interrupt request due to a receive interrupt from the RCAN-ET cannot be sent to
the CPU in this case. Figure 22.15 shows a DMAC transfer flowchart.
DMAC initialization
DMAC enable register setting
DMAC register information setting
: Settings by user
: Processing by hardware
Message reception in RCAN-ET
mailbox 0
DMAC activation
No
End of DMAC transfer?
Yes
RXPR and RFPR flags clearing
DMAC interrupt
No
enabled?
Yes
Interrupt to CPU
END
22.15 DMAC Transfer Flowchart
Rev. 1.00 Jun. 26, 2008 Page 1076 of 1692
REJ09B0393-0100