SH7280 Datasheet, PDF (340/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 9 Bus State Controller (BSC)
9.5.2 Normal Space Interface
(1) Basic Timing
For access to a normal space, this LSI uses strobe signal output in consideration of the fact that
mainly static RAM will be directly connected. When using SRAM with a byte-selection pin, see
section 9.5.8, SRAM Interface with Byte Selection. Figure 9.2 shows the basic timings of normal
space access. A no-wait normal access is completed in two cycles. The BS signal is asserted for
one cycle to indicate the start of a bus cycle.
T1
T2
CK
A25 to A0
CSn
RD/WR
Read
RD
D15 to D0
RD/WR
Write
WEn
D15 to D0
BS
DACKn^*
Note: * The waveform for DACKn is when active low is specified.
Figure 9.2 Normal Space Basic Access Timing (Access Wait 0)
Rev. 1.00 Jun. 26, 2008 Page 310 of 1692
REJ09B0393-0100