SH7280 Datasheet, PDF (1409/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 25 USB Function Module
25.11.4 Assigning Interrupt Source for EP0
Interrupt sources (bits 0 to 3) for EP0 that are assigned to USBIFR0 of this module must be
assigned to the same interrupt pin using USBISR0.
25.11.5 Clearing FIFO when Setting DMA/DTC Transfer
Clearing the endpoint 1 data register (USBEPDR1) is impossible when DMA/DTC transfer is
enabled (USBDMAR/EP1DMAE = 1) for endpoint 1. To clear this register, cancel DMA/DTC
transfer.
25.11.6 Manual Reset for DMA/DTC Transfer
Do not input a manual reset during DMA/DTC transfer for endpoints 1 and 2. Correct operation
cannot be guaranteed.
25.11.7 USB Clock
Wait for the USB clock settling time and then cancel the module stop setting for the USB function
module.
25.11.8 Using TR Interrupt
Note that the following when using the transfer request interrupt (TR interrupt) for interrupt-IN
transfer of EP0i/EP2/EP3.
The TR interrupt flag is set when the IN token is sent from the USB host and there is no data in
the FIFO of the EP. However, TR interrupts occur continuously at the timing shown in figure
25.28. Make sure that no malfunction occurs in these cases.
Note:
This module checks NAK acknowledgement if there is no data in the FIFO of the EP
when receiving the IN token. However the TR interrupt flag is set after transmitting the
NAK handshake. Therefore, when writing the USBTRG/PKTE bit is later than the next IN
token, the TR interrupt flag is set again.
Rev. 1.00 Jun. 26, 2008 Page 1379 of 1692
REJ09B0393-0100