SH7280 Datasheet, PDF (1406/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 25 USB Function Module
USB function
IN token reception
Valid data
in EP2 FIFO?
YES
NO
NACK
Data transmission to host
ACK
DTC function
Application
Set I[3:0] bits in SR
Clear RRS bit in DTCCR to 0
Set transfer information
(MRA, MRB, SAR, DAR)
Set the start address of transfer
information in DTC vector table
Set DTCE0 bit in DTCERA to 1
Is there data
NO
for transmission
to host?
YES
Enable EP2 FIFO empty interrupt
(USBIER0/EP2 EMPTY = 1)
Space
in EP2 FIFO?
NO
YES
Set EP2 empty status
(USBIFR0/EP2
EMPTY = 1)
Interrupt request to CPU
Disable EP2 FIFO
empty interrupt
(USBIER0/EP2 EMPTY = 0)
Clear RRS bit in DTCCR to 0
Clear EP2 empty status
(USBIFR0/EP2
EMPTY = 0)
Set transfer information
[1]
(CRA, CRB)
Set RRS bit in DTCCR to 1
Activate DTC
DTC transfer
request
Clear TXF bit in USDTENDRR
and set bits 3 to 0 in IPR18
(enable interrupts)
Set EP2DMAE bit in USBDMAR
to 1
Interrupt request
DTC transfer end
Clear DTCE1 bit in DTCERA
Transmit data transfer end
interrupt
to CPU
Clear EP2DMAE bit in USBDMAR
to 0 and set bits 3 to 0 in IPR18
(disable interrupts)
[1] In block transfer mode, the block size set in CRA should be 64 bytes or less.
[2] When the transmit data size is a multiple of 64 bytes, this step can be omitted.
Write 1 to EP2 packet
enable bit
[2]
(USBTRG/EP2 PKTE = 1)
Figure 25.26 Example of DTC Transfer for Bulk-IN Transfer (EP2)
(When Transmit Data Size Cannot be Determined Before Receiving IN Token)
Rev. 1.00 Jun. 26, 2008 Page 1376 of 1692
REJ09B0393-0100