SH7280 Datasheet, PDF (509/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Initial
Bit
Bit Name Value R/W Description
0
TGFA
0
R/(W)*¹ Input Capture/Output Compare Flag A
Status flag that indicates the occurrence of TGRA input
capture or compare match. Only 0 can be written, for
flag clearing.
[Clearing conditions]
• When DMAC is activated by TGIA interrupt.
• When DTC is activated by TGIA interrupt, and the
DISEL bit of MRB in DTC is cleared to 0.
• When 0 is written to TGFA after reading
TGFA = 1*²
[Setting conditions]
• When TCNT = TGRA and TGRA is functioning as
output compare register
• When TCNT value is transferred to TGRA by input
capture signal and TGRA is functioning as input
capture register
Notes: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.
2. After reading 1, when the next flag set is generated before writing 0, the flag will not be
cleared by writing 0. Read 1 again and write 0 in this case.
Rev. 1.00 Jun. 26, 2008 Page 479 of 1692
REJ09B0393-0100