SH7280 Datasheet, PDF (908/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 17 Serial Communication Interface with FIFO (SCIF)
17.6.6 Receive Data Sampling Timing and Receive Margin (Asynchronous Mode)
The SCIF operates on a base clock with a frequency of 16 times the transfer rate.* In reception,
the SCIF synchronizes internally with the fall of the start bit, which it samples on the base clock.
Receive data is latched at the rising edge of the eighth base clock pulse. The timing is shown in
figure 17.17.
Note: * This is an example when ABCS = 0 in SCSEMR. When ABCS = 1, a frequency of 8 times
the bit rate becomes the basic clock, and receive data is sampled at the fourth rising edge
of the basic clock.
Base clock
Receive data
(RxD)
Synchronization
sampling timing
16 clocks
8 clocks
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5
–7.5 clocks
+7.5 clocks
Start bit
D0
D1
Data sampling
timing
Figure 17.17 Receive Data Sampling Timing in Asynchronous Mode
Rev. 1.00 Jun. 26, 2008 Page 878 of 1692
REJ09B0393-0100