SH7280 Datasheet, PDF (277/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 9 Bus State Controller (BSC)
BREQ
BACK
WAIT
Bus
mastership
controller
Wait
controller
CMNCR
CS0WCR
CS7WCR
CS0 to CS7
MD1, MD0
Area
controller
CS0BCR
CS7BCR
A25 to A0*,
D31 to D0*
BS, RD/WR,
RD, WRx,
RASL, RASU*,
CASL, CASU*,
CKE, DQMxx, AH,
REFOUT
Memory
controller
Refresh
controller
SDCR
RTCSR
RTCNT
Comparator
RTCOR
BSC
[Legend]
CMNCR: Common control register
CSnWCR: CSn space wait control register (n = 0 to 7)
CSnBCR: CSn space bus control register (n = 0 to 7)
SDCR: SDRAM control register
RTCSR: Refresh timer control/status register
RTCNT: Refresh timer counter
RTCOR: Refresh time constant register
Note * A20 to A0, D15 to D0, RASL, and CASL are available only in the SH7285 and the SH7243.
Figure 9.1 Block Diagram of BSC
Rev. 1.00 Jun. 26, 2008 Page 247 of 1692
REJ09B0393-0100