SH7280 Datasheet, PDF (190/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 6 Interrupt Controller (INTC)
6.9 Data Transfer with Interrupt Request Signals
Interrupt request signals can be used to trigger the following data transfer.
• Only the DMAC is activated and no CPU interrupt occurs.
• Only the DTC is activated and a CPU interrupt may occur depending on the DTC setting.
Interrupt sources that are designated to activate the DMAC are masked without being input to the
INTC. The mask condition is as follows:
Mask condition = DME • (DE0 • interrupt source select 0 + DE1 • interrupt source select 1
+ DE2 • interrupt source select 2 + DE3 • interrupt source select 3 +
DE4 • interrupt source select 4 + DE5 • interrupt source select 5 + DE6
• interrupt source select 6 + DE7 • interrupt source select 7)
Here, DME is bit 0 in DMAOR of the DMAC, and DEn (n = 0 to 7) is bit 0 in CHCR0 to CHCR7
of the DMAC. For details, see section 10, Direct Memory Access Controller (DMAC).
The INTC masks a CPU interrupt when the corresponding DTCE bit is 1. The DTCE clearing
condition and interrupt source flag clearing condition are as follows:
DTCE clearing condition = DTC transfer end • DTCECLR
Interrupt source flag clearing condition = DTC transfer end • DTCECLR + DMAC transfer
end
However, DTCECLR = DISEL + counter value of 0
Rev. 1.00 Jun. 26, 2008 Page 160 of 1692
REJ09B0393-0100