SH7280 Datasheet, PDF (949/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 18 Synchronous Serial Communication Unit (SSU)
(3) Data Reception
Figure 18.15 shows an example of reception operation, and figure 18.16 shows a flowchart
example of data reception. When receiving data, the SSU operates as shown below.
After setting the RE bit in SSER to 1, the SSU starts data reception.
In master mode, the SSU outputs a transfer clock and receives data. In slave mode, when a transfer
clock is input to the SSCK pin, the SSU receives data in synchronization with the transfer clock.
When 1-frame data has been received, the RDRF bit in SSSR is set to 1 and the receive data is
stored in SSRDR. At this time, if the RIE bit is set to 1, an RXI interrupt is generated. The RDRF
bit is automatically cleared to 0 by reading SSRDR.
When SSU is set in slave mode and receive data continuously, read SSRDR before starting
reception of a next frame. When the next reception starts before RDRF is cleared to 0, all
subsequent data is not guaranteed.
SSCK
SSO
Bit 0
Bit 7
Bit 0
Bit 7
Bit 0
1 frame
1 frame
RDRF
LSI operation
User operation
Dummy-read SSRDR
RXI interrupt
generated
Read data
from SSRDR
RXI interrupt
generated
Read data
from SSRDR
Figure 18.15 Example of Reception Operation
(Clock Synchronous Communication Mode)
Bit 7
RXI interrupt
generated
Rev. 1.00 Jun. 26, 2008 Page 919 of 1692
REJ09B0393-0100