SH7280 Datasheet, PDF (1387/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 25 USB Function Module
25.5.4 EP1 Bulk-OUT Transfer (Dual FIFOs)
EP1 has two 64-byte FIFOs, but the user can perform data reception and receive data reads
without being aware of this dual-FIFO configuration.
When one FIFO is full after reception is completed, the USBIFR0/EP1 FULL bit is set. After the
first receive operation into one of the FIFOs when both FIFOs are empty, the other FIFO is empty,
and so the next packet can be received immediately. When both FIFOs are full, NACK is returned
to the host automatically. When reading of the receive data is completed following data reception,
1 is written to the USBTRG/EP1 RDFN bit. This operation empties the FIFO that has just been
read, and makes it ready to receive the next packet.
USB function
OUT token reception
Application
Space
in EP1 FIFO?
Yes
No
NACK
Data reception from host
ACK
Set EP1 FIFO full status
(USBIFR0/EP1 FULL = 1)
Interrupt request
Read USBEP1 receive data
size register (USBEPSZ1)
Read data from USBEP1
data register (USBEPDR1)
Write 1 to EP1 read
complete bit
(USBTRG/EP1 RDFN = 1)
Both
EP1 FIFOs empty?
No Interrupt request
Yes
Clear EP1 FIFO full status
(USBIFR0/EP1 FULL = 0)
Figure 25.10 EP1 Bulk-OUT Transfer Operation
Rev. 1.00 Jun. 26, 2008 Page 1357 of 1692
REJ09B0393-0100