SH7280 Datasheet, PDF (925/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Initial
Bit
Bit Name Value R/W
3
SCSATS 0
R/W
2
SSODTS 0
R/W
1, 0 
All 0
R
Section 18 Synchronous Serial Communication Unit (SSU)
Description
Selects the assertion timing of the SCS pin (valid in
SSU and master mode).
0:
Min.
values
of
t
LEAD
and
t
LAG
are
1/2
×
t
SUcyc
1: Min. values of t_LEAD and t_LAG are 3/2 × t_SUcyc
Selects the data output timing of the SSO pin (valid in
SSU and master mode)
0: While BIDE = 0, MSS = 1, and TE = 1 or while BIDE
= 1, TE = 1, and RE = 0, the SSO pin outputs data
1: While BIDE = 0, MSS = 1, and TE = 1 or while BIDE
= 1, TE = 1, and RE = 0, the SSO pin outputs data
while the SCS pin is driven low
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 1.00 Jun. 26, 2008 Page 895 of 1692
REJ09B0393-0100