SH7280 Datasheet, PDF (1644/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 31 Electrical Characteristics
CK
A25 to A0
A12/A11^*1
Tr
Tc1
Tcw
t_AD1
t_AD1
Row address
Column address
t_AD1
t_AD1
t_AD1
READA command
Td1
Tde
t_AD1
CSn
RD/WR
RASU/L
CASU/L
DQMxx
t_CSD1
t_RWD1
t_RASD1
t_RASD1
t_CASD1
t_CASD1
t_DQMD1
D31 to D0
BS
t_BSD
t_BSD
t_CSD1
t_RWD1
t_DQMD1
t_RDS2
tRDH2
CKE
DACKn
TENDn*²
t_DACD
(High)
t_DACD
Notes: 1. An address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn and TENDn is when active low is specified.
Figure 31.19 Synchronous DRAM Single Read Bus Cycle
(Auto Precharge, CAS Latency 2, WTRCD = 0 Cycle, WTRP = 0 Cycle)
Rev. 1.00 Jun. 26, 2008 Page 1614 of 1692
REJ09B0393-0100