SH7280 Datasheet, PDF (91/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 2 CPU
2.5 Processing States
The CPU has five processing states: reset, exception handling, bus-released, program execution,
and power-down. Figure 2.6 shows the transitions between the states.
Power-on reset from any state
Manual reset from any state
except software standby mode
Power-on reset state
Manual reset state
Reset canceled
Reset state
Interrupt source or
DMA address error occurs
Exception
handling state
Bus request
cleared
Bus request
generated
Exception
handling
source
occurs
Exception
handling
ends
Bus-released state
Bus request
cleared
Bus request
generated
Program execution state
Bus request Bus request
generated
cleared
STBY bit cleared
for SLEEP
instruction
STBY bit set
for SLEEP
instruction
Sleep mode
Software standby mode
Figure 2.6 Transitions between Processing States
Power-down state
Rev. 1.00 Jun. 26, 2008 Page 61 of 1692
REJ09B0393-0100