SH7280 Datasheet, PDF (230/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 8 Data Transfer Controller (DTC)
8.2.1 DTC Mode Register A (MRA)
MRA selects DTC operating mode. MRA cannot be accessed directly by the CPU.
Bit: 7
6
5
4
3
2
1
0
MD[1:0]
Sz[1:0]
SM[1:0]
-
-
Initial value: *
*
*
*
*
*
*
*
R/W: -
-
-
-
-
-
-
-
* : Undefined
Initial
Bit Bit Name Value
R/W
7, 6 MD[1:0] Undefined 
5, 4 Sz[1:0] Undefined 
3, 2 SM[1:0] Undefined 
Description
DTC Mode 1 and 0
Specify DTC transfer mode.
00: Normal mode
01: Repeat mode
10: Block transfer mode
11: Setting prohibited
DTC Data Transfer Size 1 and 0
Specify the size of data to be transferred.
00: Byte-size transfer
01: Word-size transfer
10: Longword-size transfer
11: Setting prohibited
Source Address Mode 1 and 0
Specify an SAR operation after a data transfer.
0x: SAR is fixed
(SAR write-back is skipped)
10: SAR is incremented after a transfer
(by 1 when Sz1 and Sz0 = B'00; by 2 when Sz1 and
Sz0 = B'01; by 4 when Sz1 and Sz0 = B'10)
11: SAR is decremented after a transfer
(by 1 when Sz1 and Sz0 = B'00; by 2 when Sz1 and
Sz0 = B'01; by 4 when Sz1 and Sz0 = B'10)
Rev. 1.00 Jun. 26, 2008 Page 200 of 1692
REJ09B0393-0100