SH7280 Datasheet, PDF (819/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 16 Serial Communication Interface (SCI)
• Transmitting Serial Data (Asynchronous Mode)
Figure 16.4 shows a sample flowchart for serial transmission. Use the following procedure for
serial data transmission after enabling the SCI for transmission.
Start of transmission
Read TDRE flag in SCSSR
No
TDRE = 1?
Yes
Write transmit data in SCTDR
and clear TDRE bit in SCSSR to 0
No
All data transmitted?
Yes
Read TEND flag in SCSSR
No
TEND = 1?
Yes
No
Break output?
Yes
Clear SPB0DT to 0 and
set SPB0IO to 1
Clear TE bit in SCSCR to 0
End of transmission
[1] SCI status check and transmit data
write:
Read SCSSR and check that the
TDRE flag is set to 1, then write
transmit data to SCTDR, and clear
the TDRE flag to 0.
[2] Serial transmission continuation
procedure:
To continue serial transmission, read
1 from the TDRE flag to confirm that
writing is possible, then write data to
SCTDR, and then clear the TDRE
flag to 0.
When the DTC is activated by a
transmit data empty interrupt (TXI)
request to write data to SCTDR,
clearing of the TDRE flag is automatic
except when the transfer counter = 0
or DISEL = 1 as shown in the
flowchart of DTC operation in section
8, Data Transfer Controller (DTC).
When the transfer counter = 0 or
DISEL = 1, clear the TDRE flag in the
interrupt handling routine.
[3] Break output at the end of serial
transmission:
To output a break in serial
transmission, clear the SPB0DT bit to
0 and set the SPB0IO bit to 1 in
SCSPTR, then clear the TE bit in
SCSCR to 0.
Figure 16.4 Sample Flowchart for Transmitting Serial Data
Rev. 1.00 Jun. 26, 2008 Page 789 of 1692
REJ09B0393-0100