SH7280 Datasheet, PDF(1092/1726 Page) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

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SH7280 Datasheet, PDF (1092/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

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Section 22 Controller Area Network (RCAN-ET) (SH7286 Only)

Power On/SW Reset*1

Reset Sequence

Configuration Mode

MCR[0] = 1

(automatically in hardware reset only)

IRR[0] = 1, GSR[3] = 1 (automatically)

No

GSR[3] = 0?

Yes

clear IRR[0] Bit

Configure MCR[15]

Clear Required IMR Bits

Mailbox Setting

(STD-ID, EXT-ID, LAFM, DLC,

RTR, IDE, MBC, MBIMR, DART,

ATX, NMC, Message-Data)*2

RCAN-ET is in Tx_Rx Mode

Set TXPR to start transmission

or stay idle to receive

Transmission_Reception

(Tx_Rx) Mode

Detect 11 recessive bits and

Join the CAN bus activity

Set Bit Timing (BCR)

Clear MCR[0]

Receive*3

Transmit*3

Notes: 1. SW reset could be performed at any time by setting MCR[0] = 1.

2. Mailboxes are comprised of RAMs, therefore, please initialise all the mailboxes enabled by MBC.

3. If there is no TXPR set, RCAN-ET will receive the next incoming message.

If there is a TXPR(s) set, RCAN-ET will start transmission of the message and will be arbitrated by the CAN bus.

If it loses the arbitration, it will become a receiver.

Figure 22.8 Reset Sequence

Rev. 1.00 Jun. 26, 2008 Page 1062 of 1692

REJ09B0393-0100

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