SH7280 Datasheet, PDF (293/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 9 Bus State Controller (BSC)
Bit
10, 9
8 to 0
Bit Name
BSZ[1:0]

Initial
Value
01*
All 0
R/W Description
R/W Data Bus Width Specification
Specify the data bus widths of spaces.
00: Reserved (setting prohibited)
01: 8-bit size
10: 16-bit size
11: 32-bit size (only in SH7286, Setting prohibited both
in the SH7285 and SH7243)
For MPX-I/O, selects bus width by address.
Notes:
1. If area 5 is specified as MPX-I/O, the bus
width can be specified as 8 bits or 16 bits
by the address according to the SZSEL bit
in CS5WCR by specifying the BSZ[1:0]
bits to 11. The fixed bus width can be
specified as 8 bits or 16 bits.
2. The initial data bus width for areas 0 to 7
is specified by external pins. In on-chip
ROM-disabled mode, writing to the BSZ1
and BSZ0 bits in CS0BCR is ignored, but
the bus width settings in CS1BCR to
CS7BCR can be modified. In on-chip
ROM-enabled mode, the bus width
settings in CS0BCR to CS7BCR can be
modified.
3. If area 2 or area 3 is specified as SDRAM
space, the bus width can be specified as
16 bits only.
4. If area 0 or 4 is specified as clock-
synchronous burst ROM space, the bus
width can be specified as 16 bits only.
R
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 1.00 Jun. 26, 2008 Page 263 of 1692
REJ09B0393-0100