SH7280 Datasheet, PDF (911/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 18 Synchronous Serial Communication Unit (SSU)
Section 18 Synchronous Serial Communication Unit (SSU)
This LSI (SH7286 or SH7285) has an independent synchronous serial communication unit (SSU)
channel. The SSU has master mode in which this LSI outputs clocks as a master device for
synchronous serial communication and slave mode in which clocks are input from an external
device for synchronous serial communication. Synchronous serial communication can be
performed with devices having different clock polarity and clock phase.
18.1 Features
• Choice of SSU mode and clock synchronous mode
• Choice of master mode and slave mode
• Choice of standard mode and bidirectional mode
• Synchronous serial communication with devices with different clock polarity and clock phase
• Choice of 8/16/32-bit width of transmit/receive data
• Full-duplex communication capability
The shift register is incorporated, enabling transmission and reception to be executed
simultaneously.
• Consecutive serial communication
• Choice of LSB-first or MSB-first transfer
• Choice of a clock source
Pφ/4, Pφ/8, Pφ/16, Pφ/32, Pφ/64, Pφ/128, Pφ/256, or an external clock
• Five interrupt sources
Transmit end, transmit data register empty, receive data full, overrun error, and conflict error.
The data transfer controller (DTC) can be activated by a transmit data register empty request or
a receive data full request to transfer data.
• Module standby mode can be set
SCISSU0A_000120020900
Rev. 1.00 Jun. 26, 2008 Page 881 of 1692
REJ09B0393-0100