SH7280 Datasheet, PDF (460/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 10 Direct Memory Access Controller (DMAC)
T1 T2 Taw T1 T2
CK
Address
CS
RD
Data
WEn
DACKn
(Active low)
TEND
(Active low)
WAIT
Note: TEND is asserted for the last unit of DMA transfer. If a transfer unit
is divided into multiple bus cycles and the CS is negated between
the bus cycles, TEND is also divided.
Figure 10.18 BSC Normal Memory Access
(No Wait, Idle Cycle 1, Longword Access to 16-Bit Device)
Rev. 1.00 Jun. 26, 2008 Page 430 of 1692
REJ09B0393-0100