SH7280 Datasheet, PDF (888/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 17 Serial Communication Interface with FIFO (SCIF)
(3) Transmitting and Receiving Data
• SCIF Initialization (Asynchronous Mode)
Before transmitting or receiving, clear the TE and RE bits to 0 in the serial control register
(SCSCR), then initialize the SCIF as follows.
When changing the operating mode or the communication format, always clear the TE and RE bits
to 0 before following the procedure given below. Clearing TE to 0 initializes the transmit shift
register (SCTSR). Clearing TE and RE to 0, however, does not initialize the serial status register
(SCFSR), transmit FIFO data register (SCFTDR), or receive FIFO data register (SCFRDR), which
retain their previous contents. Clear TE to 0 after all transmit data has been transmitted and the
TEND flag in the SCFSR is set. The TE bit can be cleared to 0 during transmission, but the
transmit data goes to the Mark state after the bit is cleared to 0. Set the TFRST bit in SCFCR to 1
and reset SCFTDR before TE is set again to start transmission.
When an external clock is used, the clock should not be stopped during initialization or subsequent
operation. SCIF operation becomes unreliable if the clock is stopped.
Figure 17.3 shows a sample flowchart for initializing the SCIF.
Start of initialization
Clear TE and RE bits in SCSCR to 0
Set TFRST and RFRST bits in SCFCR to 1
After reading ER, DR, and BRK flags in SCFSR,
and each flag in SCLSR, write 0 to clear them
Set CKE1 and CKE0 in SCSCR
(leaving TIE, RIE, TE, and RE bits cleared to 0)
[1]
Set data transfer format in SCSMR
[2]
Set value in SCBRR
[3]
Set ABCS bit in SCSEMR
Set RTRG[1:0] and TTRG[1:0], and MCE in
SCFCR, and clear TFRST and RFRST
[1] Set the clock selection in SCSCR.
Be sure to clear bits TIE, RIE, TE,
and RE to 0.
[2] Set the data transfer format in
SCSMR.
[3] Write a value corresponding to the
bit rate into SCBRR. (Not
necessary if an external clock is
used.)
[4] Set the TE bit or RE bit in SCSCR
to 1. Also set the RIE, REIE, and
TIE bits. Setting the TE and RE bits
enables the TxD and RxD pins to be
used.
When transmitting, the SCIF will go
to the mark state; when receiving,
it will go to the idle state, waiting for
a start bit.
Set TE and RE bits in SCSCR to 1,
and set TIE, RIE, and REIE bits
[4]
End of initialization
Figure 17.3 Sample Flowchart for SCIF Initialization
Rev. 1.00 Jun. 26, 2008 Page 858 of 1692
REJ09B0393-0100