SH7280 Datasheet, PDF(81/1726 Page) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

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SH7280 Datasheet, PDF (81/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

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Section 2 CPU

Instruction

Instruction Code

Operation

Execu-

tion

Cycles

T Bit

Compatibility

SH2,

SH2E SH4 SH-2A

MOVRT Rn

0000nnnn00111001 ~T â Rn

1

ï£§

Yes

MOVT Rn

0000nnnn00101001 T â Rn

1

ï£§ Yes Yes Yes

MOVU.B @(disp12,Rm),Rn 0011nnnnmmmm0001 (disp + Rm) â

1

ï£§

Yes

zero extension â Rn

1000dddddddddddd

MOVU.W @(disp12,Rm),Rn 0011nnnnmmmm0001 (disp Ã 2 + Rm) â

1

ï£§

Yes

zero extension â Rn

1001dddddddddddd

NOTT

0000000001101000 ~T â T

1

Ope-

Yes

ration

result

PREF @Rn

0000nnnn10000011 (Rn) â operand cache

1

ï£§

Yes Yes

SWAP.B Rm,Rn

0110nnnnmmmm1000 Rm â swap lower 2 bytes â 1

Rn

ï£§ Yes Yes Yes

SWAP.W Rm,Rn

0110nnnnmmmm1001 Rm â swap upper and lower 1

words â Rn

ï£§ Yes Yes Yes

XTRCT Rm,Rn

0010nnnnmmmm1101 Middle 32 bits of Rm:Rn â Rn 1

ï£§ Yes Yes Yes

Rev. 1.00 Jun. 26, 2008 Page 51 of 1692

REJ09B0393-0100

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