SH7280 Datasheet, PDF (1541/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 28 Power-Down Modes
Table 28.4 Register States in Software Standby Mode
Module Name
Registers Whose
Initialized Registers Content is Retained
Interrupt controller (INTC)

All registers
Clock pulse generator (CPG)

All registers
User break controller (UBC)

All registers
Bus state controller (BSC)

All registers
A/D converter (ADC)
*

I/O port

All registers
User debugging interface (H-UDI)

All registers
Serial communication interface with FIFO
(SCIF)
SCSEMR
All registers except
SCSEMR
Direct memory access controller (DMAC)

All registers
Multi-function timer pulse unit 2 (MTU2)

All registers
Multi-function timer pulse unit 2S (MTU2S)

All registers
Port output enable 2 (POE2)

All registers
Compare match timer (CMT)
All registers

I²C bus interface 3 (IIC3)
BC2 and BC0 bits in Other than BC[2:0] bits in
ICMR register
ICMR
D/A converter (DAC)

All registers
Serial communication interface (SCI)

All registers
USB function module (USB)

All registers
Synchronous serial communication interface 
(SSU)
All registers
Controller area network (RCAN-IF)

All registers
Note: * The A/D converter register values become undetermined.
The procedure for switching to software standby mode is as follows:
1. Clear the TME bit in the WDT's timer control register (WTCSR) to 0 to stop the WDT.
2. Set the WDT's timer counter (WTCNT) to 0 and the CKS[2:0] bits in WTCSR to appropriate
values to secure the specified oscillation settling time.
3. After setting the STBY bit in STBCR to 1, read STBCR. Then, execute a SLEEP instruction.
Rev. 1.00 Jun. 26, 2008 Page 1511 of 1692
REJ09B0393-0100