SH7280 Datasheet, PDF (412/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 10 Direct Memory Access Controller (DMAC)
• Transfer request acknowledge and transfer end signals: Active levels for DACK and TEND
can be set independently.
• Support of reload functions in DMA transfer information registers: DMA transfer using the
same information as the current transfer can be repeated automatically without specifying the
information again. Modifying the reload registers during DMA transfer enables next DMA
transfer to be done using different transfer information. The reload function can be enabled or
disabled independently in each channel.
Figure 10.1 shows the block diagram of the DMAC.
On-chip
memory
On-chip
peripheral module
Iteration
control
Register
control
DMA transfer request signal
DMA transfer acknowledge signal
Interrupt controller
Start-up
control
HEIn
DEIn
Request
priority
control
External ROM
External RAM
External device
(memory mapped)
External device
(with acknowledge)
Bus
interface
Bus state
controller
RDMATCR_n
DMATCR_n
RSAR_n
SAR_n
RDAR_n
DAR_n
CHCR_n
DMAOR
DMARS0
to DMARS3
DMAC module
DREQ0 to DREQ3*
DACK0 to DACK3,
TEND0, TEND1
[Legend]
RDMATCR: DMA reload transfer count register
DMATCR: DMA transfer count register
RSAR: DMA reload source address register
SAR:
DMA source address register
RDAR: DMA reload destination address register
DAR:
DMA destination address register
CHCR:
DMA channel control register
DMAOR:
DMA operation register
DMARS0 to DMARS3: DMA extension resource selectors 0 to 3
HEIn:
DMA transfer half-end interrupt request to the CPU
DEIn:
DMA transfer end interrupt request to the CPU
n = 0 to 7
Notes: * DREQ0 and DREQ1 (SH7285 and SH7243)
DREQ0 to DREQ3 (SH7286)
Figure 10.1 Block Diagram of DMAC
Rev. 1.00 Jun. 26, 2008 Page 382 of 1692
REJ09B0393-0100