SH7280 Datasheet, PDF (324/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 9 Bus State Controller (BSC)
Bit
17, 16
15, 14
13
12
11
Bit Name
A2COL[1:0]
Initial
Value
00

All 0
DEEP
0
SLOW
0
RFSH
0
R/W Description
R/W Number of Bits of Column Address for Area 2
Specify the number of bits of column address for
area 2.
00: 8 bits
01: 9 bits
10: 10 bits
11: Reserved (setting prohibited)
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W Deep Power-Down Mode
This bit is valid for low-power SDRAM. If the RFSH or
RMODE bit is set to 1 while this bit is set to 1, the deep
power-down entry command is issued and the low-
power SDRAM enters deep power-down mode.
0: Self-refresh mode
1: Deep power-down mode
R/W Low-Frequency Mode
Specifies the output timing of command, address, and
write data for SDRAM and the latch timing of read data
from SDRAM. Setting this bit makes the hold time for
command, address, write and read data extended for
half cycle (output or read at the falling edge of CK).
This mode is suitable for SDRAM with low-frequency
clock.
0: Command, address, and write data for SDRAM is
output at the rising edge of CK. Read data from
SDRAM is latched at the rising edge of CK.
1: Command, address, and write data for SDRAM is
output at the falling edge of CK. Read data from
SDRAM is latched at the falling edge of CK.
R/W Refresh Control
Specifies whether or not the refresh operation of the
SDRAM is performed.
0: No refresh
1: Refresh
Rev. 1.00 Jun. 26, 2008 Page 294 of 1692
REJ09B0393-0100