SH7280 Datasheet, PDF (914/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 18 Synchronous Serial Communication Unit (SSU)
18.3 Register Descriptions
The SSU has the following registers. For details on the addresses of these registers and the states
of these registers in each processing state, see section 30, List of Registers.
Table 18.2 Register Configuration
Register Name
SS control register H
SS control register L
SS mode register
SS enable register
SS status register
SS control register 2
SS transmit data register 0
SS transmit data register 1
SS transmit data register 2
SS transmit data register 3
SS receive data register 0
SS receive data register 1
SS receive data register 2
SS receive data register 3
Abbrevia-
tion
R/W Initial value Address
Access Size
SSCRH
R/W H'0D
H'FFFFB000 8, 16
SSCRL
R/W H'00
H'FFFFB001 8
SSMR
R/W H'00
H'FFFFB002 8, 16
SSER
R/W H'00
H'FFFFB003 8
SSSR
R/W H'04
H'FFFFB004 8, 16
SSCR2
R/W H'00
H'FFFFB005 8
SSTDR0 R/W H'00
H'FFFFB006 8, 16
SSTDR1 R/W H'00
H'FFFFB007 8
SSTDR2 R/W H'00
H'FFFFB008 8, 16
SSTDR3 R/W H'00
H'FFFFB009 8
SSRDR0 R
H'00
H'FFFFB00A 8, 16
SSRDR1 R
H'00
H'FFFFB00B 8
SSRDR2 R
H'00
H'FFFFB00C 8, 16
SSRDR3 R
H'00
H'FFFFB00D 8
Rev. 1.00 Jun. 26, 2008 Page 884 of 1692
REJ09B0393-0100