SH7280 Datasheet, PDF (33/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 1 Overview
Items
Specification
ROM cache
• Instruction/data separation system
• Instruction prefetch cache: Full/set associative
• Instruction prefetch miss cache: Full/set associative
• Data cache: Full/set associative
• Line size: 16 bytes
• Hardware prefetch function (continuous/branch prefetch)
Interrupt controller
(INTC)
• Nine external interrupt pins (NMI and IRQ7 to IRQ0)
• On-chip peripheral interrupts: Priority level set for each module
• 16 priority levels available
• Register bank enabling fast register saving and restoring in interrupt
processing
Bus state controller
(BSC)
• Address space divided into eight areas (0 to 7), each a maximum of 64
Mbytes
• External bus: 8, 16, or 32 bits (32-bit bus available only in SH7286)
• The following features settable for each area independently
 Supports both big endian and little endian for data access
 Bus size (8, 16, or 32 bits): Available sizes depend on the area.
 Number of access wait cycles (different wait cycles can be
specified for read and write access cycles in some areas)
 Idle wait cycle insertion (between same area access cycles or
different area access cycles)
• SDRAM refresh
Auto refresh or self refresh mode selectable
• SDRAM burst access
Direct memory access • Eight channels; external request available for four (SH7286) and two
controller (DMAC)
(SH7285 and SH7243) of them
• Can be activated by on-chip peripheral modules
• Burst mode and cycle steal mode
• Intermittent mode available (16 and 64 cycles supported)
• Transfer information can be automatically reloaded
Rev. 1.00 Jun. 26, 2008 Page 3 of 1692
REJ09B0393-0100