SH7280 Datasheet, PDF (852/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 17 Serial Communication Interface with FIFO (SCIF)
17.3 Register Descriptions
The SCIF has the following registers.
Table 17.2 Register Configuration
Channel Register Name
Abbreviation R/W
Initial Value Address
Access
Size
3
Serial mode register_3
SCSMR_3
R/W
H'0000
H'FFFE9800 16
Bit rate register_3
SCBRR_3
R/W
H'FF
H'FFFE9804 8
Serial control register_3
SCSCR_3
R/W
H'0000
H'FFFE9808 16
Transmit FIFO data register_3 SCFTDR_3
Serial status register_3
SCFSR_3
W
Undefined H'FFFE980C 8
R/(W)*¹ H'0060
H'FFFE9810 16
Receive FIFO data register_3 SCFRDR_3 R
Undefined H'FFFE9814 8
FIFO control register_3
SCFCR_3
R/W
H'0000
H'FFFE9818 16
FIFO data count register_3
SCFDR_3
R
H'0000
H'FFFE981C 16
Serial port register_3
Line status register_3
SCSPTR_3
SCLSR_3
R/W H'0050
R/(W)*² H'0000
H'FFFE9820 16
H'FFFE9824 16
Serial extended mode
register_3
SCSEMR_3 R/W H'00
H'FFFE9900 8
Notes: 1. Only 0 can be written to clear the flag. Bits 15 to 8, 3, and 2 are read-only bits that
cannot be modified.
2. Only 0 can be written to clear the flag. Bits 15 to 1 are read-only bits that cannot be
modified.
17.3.1 Receive Shift Register (SCRSR)
SCRSR receives serial data. Data input at the RXD pin is loaded into SCRSR in the order
received, LSB (bit 0) first, converting the data to parallel form. When one byte has been received,
it is automatically transferred to the receive FIFO data register (SCFRDR).
The CPU cannot read or write to SCRSR directly.
Bit: 7
6
5
4
3
2
1
0
Initial value: -
-
-
-
-
-
-
-
R/W: -
-
-
-
-
-
-
-
Rev. 1.00 Jun. 26, 2008 Page 822 of 1692
REJ09B0393-0100