SH7280 Datasheet, PDF (342/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 9 Bus State Controller (BSC)
CK
T1
T2
T1
T2
A25 to A0
CSn
RD/WR
Read
Write
RD
D15 to D0
WEn
D15 to D0
BS
DACKn ^*
WAIT
Note: * The waveform for DACKn is when active low is specified.
Figure 9.4 Continuous Access for Normal Space 2
Bus Width = 16 Bits, Longword Access, CSnWCR.WM Bit = 1
(Access Wait = 0, Cycle Wait = 0)
Rev. 1.00 Jun. 26, 2008 Page 312 of 1692
REJ09B0393-0100