SH7280 Datasheet, PDF (1026/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 20 A/D Converter (ADC)
ADST
ADST set*
ADF
AN0
AN1
Waiting for
conversion
A/D
conversion
(1)
A/D conversion execution
Waiting for
conversion
A/D
conversion
(2)
Waiting for
conversion
Waiting for conversion
ADST cleared*
Stop
A/D
conversion
ADF cleared*
Waiting for conversion
AN2
AN3
ADDR0
ADDR1
Waiting for
conversion
A/D
conversion
(1)
Waiting for
conversion
A/D
conversion
(2)
Waiting for conversion
A/D
conversion
(1)
Waiting for
conversion
A/D
conversion
A/D conversion result (AN0)
(1)
Waiting for conversion
Waiting for conversion
A/D conversion result (AN0)
(2)
ADDR2
A/D conversion result (AN2)
(1)
ADDR3
[Legend]
OFC: Offset canceling processing
S: Sampling
H: Holding
A/D conversion result (AN3)
(1)
[ADBYPSCR_0 settings]
OFC bit = 1
SH bit = 0
Note: * Instruction execution by software
A/D conversion result (AN2)
(2)
A/D conversion result (AN3)
(2)
Figure 20.9 Example 4 of A/D Converter Operation (Continuous Scan Mode,
Sample-and-Hold Circuit Disabled, and Offset Canceling Circuit Disabled)
Rev. 1.00 Jun. 26, 2008 Page 996 of 1692
REJ09B0393-0100