SH7280 Datasheet, PDF (838/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 16 Serial Communication Interface (SCI)
16.4.6
Multiprocessor Serial Data Reception
Figure 16.18 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in
SCSCR is set to 1, data is skipped until data with a 1 multiprocessor bit is sent. On receiving data
with a 1 multiprocessor bit, the receive data is transferred to SCRDR. An RXI interrupt request is
generated at this time. All other SCI operations are the same as in asynchronous mode. Figure
16.17 shows an example of SCI operation for multiprocessor format reception.
RXD
Start
1 bit
Data (ID1)
Stop Start
MPB bit bit
Data (Data1)
Stop
MPB bit
1
0 D0 D1
D7 1 1 0 D0 D1
D7 0
1 Idle state
(mark state)
MPIE
RDRF
SCRDR
value
ID1
MPIE = 0
RXI interrupt
request
(multiprocessor
interrupt)
generated
SCRDR data read If not this station’s ID,
and RDRF flag MPIE bit is set to 1
cleared to 0 in
again
RXI interrupt
processing routine
RXI interrupt request is
not generated,
and SCRDR retains
its state
(a) Data does not match station’s ID
RXD
Start
1 bit
Data (ID2)
Stop Start
MPB bit bit
Data (Data2)
Stop
MPB bit
1
0 D0 D1
D7 1 1 0 D0 D1
D7 0
1 Idle state
(mark state)
MPIE
RDRF
SCRDR
value
ID1
ID2
Data2
MPIE = 0
RXI interrupt
request
(multiprocessor
interrupt)
generated
SCRDR data read
and RDRF flag
cleared to 0 in
RXI interrupt
processing routine
Matches this station’s ID,
so reception continues,
and data is received in RXI
interrupt processing routine
MPIE bit is set to 1
again
(b) Data matches station’s ID
Figure 16.17 Example of SCI Operation in Reception
(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)
Rev. 1.00 Jun. 26, 2008 Page 808 of 1692
REJ09B0393-0100