SH7280 Datasheet, PDF (985/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 19 I²C Bus Interface 3 (IIC3)
SCL
SDA
(Output)
TRS
1
2
Bit 0 Bit 1
7
8
1
Bit 6 Bit 7 Bit 0
7
8
Bit 6 Bit 7
1
Bit 0
TDRE
ICDRT
Data 1
Data 2
Data 3
ICDRS
Data 1
Data 2
User
processing
[3] Write data
to ICDRT
[2] Set TRS
[3] Write data
to ICDRT
[3] Write data [3] Write data
to ICDRT
to ICDRT
Figure 19.14 Transmit Mode Operation Timing
(3) Receive Operation
In receive mode, data is latched at the rise of the transfer clock. The transfer clock is output when
MST in ICCR1 is 1, and is input when MST is 0. For receive mode operation timing, refer to
figure 19.15. The reception procedure and operations in receive mode are described below.
1. Set the ICE bit in ICCR1 to 1. Set bits CKS[3:0] in ICCR1. (Initial setting)
2. When the transfer clock is output, set MST to 1 to start outputting the receive clock.
3. When the receive operation is completed, data is transferred from ICDRS to ICDRR and
RDRF in ICSR is set. When MST = 1, the next byte can be received, so the clock is
continually output. The continuous reception is performed by reading ICDRR every time
RDRF is set. When the 8th clock rises while RDRF is 1, the overrun is detected and AL/OVE
in ICSR is set. At this time, the previous reception data is retained in ICDRR.
4. To stop receiving when MST = 1, set RCVD in ICCR1 to 1, then read ICDRR. Then, SCL is
fixed high after receiving the next byte data.
Rev. 1.00 Jun. 26, 2008 Page 955 of 1692
REJ09B0393-0100