SH7280 Datasheet, PDF (803/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 16 Serial Communication Interface (SCI)
Table 16.3 SCSMR Settings
SCSMR Settings
n
Clock Source
CKS1
CKS0
0
Pφ
0
0
1
Pφ/4
0
1
2
Pφ/16
1
0
3
Pφ/64
1
1
Note: The bit rate error in asynchronous is given by the following formula:
• When the ABCS bit in serial extended mode register (SCSEMR) is 0
Error (%) =
Pφ × 10⁶
- 1 × 100
(N + 1) × B × 64 × 2^2n-1
• When the ABCS bit in serial extended mode register (SCSEMR) is 1
Error (%) =
Pφ × 10⁶
- 1 × 100
(N + 1) × B × 32 × 2^2n-1
Tables 16.4 to 16.6 show examples of SCBRR settings in asynchronous mode, and tables 16.7 to
16.9 show examples of SCBRR settings in clock synchronous mode.
Rev. 1.00 Jun. 26, 2008 Page 773 of 1692
REJ09B0393-0100