SH7280 Datasheet, PDF (310/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 9 Bus State Controller (BSC)
Initial
Bit
Bit Name Value R/W Description
1, 0
HW[1:0] 00
R/W Number of Delay Cycles from RD, WEn Negation to
Address, CS6 Negation
Specify the number of delay cycles from RD, WEn
negation to address, and CS6 negation.
00: 0.5 cycles
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
(2) Burst ROM (Clock Asynchronous)
• CS0WCR
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
BST[1:0]
-
-
BW[1:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R R/W R/W R
R R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
W[3:0]
WM
-
-
-
-
-
-
Initial value: 0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R R/W R/W R/W R/W R/W R
R
R
R
R
R
Bit
Bit Name
31 to 22 
Initial
Value
All 0
R/W Description
R
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 1.00 Jun. 26, 2008 Page 280 of 1692
REJ09B0393-0100