SH7280 Datasheet, PDF (926/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 18 Synchronous Serial Communication Unit (SSU)
18.3.7 SS Transmit Data Registers 0 to 3 (SSTDR0 to SSTDR3)
SSTDR is an 8-bit register that stores transmit data. When 8-bit data length is selected by bits
DATS1 and DATS0 in SSCRL, SSTDR0 is valid. When 16-bit data length is selected, SSTDR0
and SSTDR1 are valid. When 32-bit data length is selected, SSTDR0 to SSTDR3 are valid. Do not
access SSTDR that is not valid.
When the SSU detects that SSTRSR is empty, it transfers the transmit data written in SSTDR to
SSTRSR and starts serial transmission. If the next transmit data has already been written to
SSTDR during serial transmission, the SSU performs consecutive serial transmission.
Although SSTDR can always be read from or written to by the CPU and DTC/DMAC, to achieve
reliable serial transmission, write transmit data to SSTDR after confirming that the TDRE bit in
SSSR is set to 1.
Bit: 7
6
5
4
3
2
1
0
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W
7 to 0
All 0
R/W
Description
Serial transmit data
Table 18.3 Setting of DATS Bits in SSCRL and Corresponding SSTDR
SSTDR0
SSTDR1
SSTDR2
SSTDR3
00
Valid
Invalid
Invalid
Invalid
01
Valid
Valid
Invalid
Invalid
DATS[1:0] Setting
10
Valid
Valid
Valid
Valid
11 (Invalid Setting)
Invalid
Invalid
Invalid
Invalid
Rev. 1.00 Jun. 26, 2008 Page 896 of 1692
REJ09B0393-0100