SH7280 Datasheet, PDF (670/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
11.7.10 Contention between TGR Write and Input Capture
If an input capture signal is generated in the T2 state of a TGR write cycle, the input capture
operation takes precedence and the write to TGR is not performed for channels 0 to 4. For channel
5, write to TGR is performed and the input capture signal is generated.
Figures 11.128 and 129 show the timing in this case.
Pφ
Address
Write signal
Input capture
signal
TCNT
TGR write cycle
T1 T2
TGR address
M
TGR
M
Figure 11.128 Contention between TGR Write and Input Capture (Channels 0 to 4)
Pφ
Address
Write signal
Input capture
signal
TCNT
TGR
TGR write cycle
T1 T2
TGR address
M
TGR write data
N
Figure 11.129 Contention between TGR Write and Input Capture (Channel 5)
Rev. 1.00 Jun. 26, 2008 Page 640 of 1692
REJ09B0393-0100