SH7280 Datasheet, PDF (762/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 14 Compare Match Timer (CMT)
14.5 Usage Notes
14.5.1 Conflict between Write and Compare-Match Processes of CMCNT
When the compare match signal is generated in the T2 cycle while writing to CMCNT, clearing
CMCNT has priority over writing to it. In this case, CMCNT is not written to. Figure 14.5 shows
the timing to clear the CMCNT counter.
Peripheral clock
(Pφ)
Address signal
Internal write signal
Counter clear signal
CMCSR write cycle
T1
T2
CMCNT
CMCNT
N
H'0000
Figure 14.5 Conflict between Write and Compare Match Processes of CMCNT
Rev. 1.00 Jun. 26, 2008 Page 732 of 1692
REJ09B0393-0100