SH7280 Datasheet, PDF (1539/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 28 Power-Down Modes
28.4 Operation
28.4.1 Sleep Mode
(1) Transition to Sleep Mode
Executing the SLEEP instruction when the STBY bit in STBCR is 0 causes a transition from the
program execution state to sleep mode. Although the CPU halts immediately after executing the
SLEEP instruction, the contents of its internal registers remain unchanged. The on-chip modules
continue to run in sleep mode. Clock pulses are output continuously on the CK pin.
(2) Canceling Sleep Mode
Sleep mode is canceled by an interrupt (NMI, IRQ, and on-chip peripheral module), DMA address
error, or reset (manual reset or power-on reset).
• Canceling with an interrupt
When an NMI, IRQ, or on-chip peripheral module interrupt occurs, sleep mode is canceled and
interrupt exception handling is executed. When the priority level of the generated interrupt is
equal to or lower than the interrupt mask level that is set in the status register (SR) of the CPU,
or the interrupt by the on-chip peripheral module is disabled on the module side, the interrupt
request is not accepted and sleep mode is not canceled.
• Canceling with a DMA or DTC address error
When a DMA or DTC address error occurs, sleep mode is canceled and DMA or DTC address
error exception handling is executed.
• Canceling with a reset
Sleep mode is canceled by a power-on reset or a manual reset.
Rev. 1.00 Jun. 26, 2008 Page 1509 of 1692
REJ09B0393-0100