SH7280 Datasheet, PDF (1020/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 20 A/D Converter (ADC)
A/D conversion execution
ADST
ADST set*
ADST automatically cleared
ADF
AN0
AN1
AN2
ADF cleared*
Simultaneous sampling
Waiting for
conversion
S
A/D
conversion
Simultaneous sampling
Waiting for conversion
Waiting for
conversion
S
H
A/D
conversion
Simultaneous sampling
Waiting for
conversion
S
H
A/D
conversion
Waiting for conversion
Waiting for conversion
AN3
Waiting for conversion
A/D
conversion
Waiting for conversion
ADDR0
A/D conversion result (AN0)
ADDR1
A/D conversion result (AN1)
ADDR2
A/D conversion result (AN2)
ADDR3
A/D conversion result (AN3)
[Legend]
OFC: Offset canceling processing
S:
Sampling
H:
Holding
Note: * Instruction execution by software
[ADBYPSCR_0 settings]
OFC bit = 1
SH bit = 1
Figure 20.4 Example 3 of A/D_0 Converter Operation (Single-Cycle Scan Mode,
Sample-and-Hold Circuit Enabled, and Offset Canceling Circuit Disabled)
Rev. 1.00 Jun. 26, 2008 Page 990 of 1692
REJ09B0393-0100