SH7280 Datasheet, PDF (1528/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 28 Power-Down Modes
28.3.2 Standby Control Register 2 (STBCR2)
STBCR2 is an 8-bit readable/writable register that controls the operation of modules in power-
down modes. STBCR2 is initialized to H'00 by a power-on reset but retains its previous value by a
manual reset or in software standby mode. Only byte access is possible.
Bit: 7
6
5
4
3
2
1
0
MSTP MSTP MSTP
10
9
8
-
-
-
MSTP
4
-
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R
R
R R/W R
Bit
7
6
5
4 to 2
1
0
Bit Name
MSTP10
Initial
Value
0
MSTP9
0
MSTP8
0

All 0
MSTP4
0

0
R/W
R/W
R/W
R/W
R
R/W
R
Description
Module Stop 10
When the MSTP10 bit is set to 1, the supply of the
clock to the H-UDI is halted.
0: H-UDI runs.
1: Clock supply to H-UDI halted.
Module Stop 9
When the MSTP9 bit is set to 1, the supply of the
clock to the UBC is halted.
0: UBC runs.
1: Clock supply to UBC halted.
Module Stop 8
When the MSTP8 bit is set to 1, the supply of the
clock to the DMAC is halted.
0: DMAC runs.
1: Clock supply to DMAC halted.
Reserved
These bits are always read as 0. The write value
should always be 0.
Module Stop 4
When the MSTP4 bit is set to 1, the supply of the
clock to the DTC is halted.
0: DTC runs.
1: Clock supply to DTC halted.
Reserved
This bit is always read as 0. The write value should
always be 0.
Rev. 1.00 Jun. 26, 2008 Page 1498 of 1692
REJ09B0393-0100