SH7280 Datasheet, PDF (1001/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 20 A/D Converter (ADC)
Section 20 A/D Converter (ADC)
This LSI includes a successive approximation type 12-bit A/D converter.
20.1 Features
• 12-bit resolution
• Input channels:
Twelve channels (SH7286)
Eight channels (SH7285 and SH7243)
• High-speed conversion
When Aφ = 50 MHz: Minimum 1.0 µs per channel
AD clock = 50 MHz, 50 conversion states
• Two operating modes
 Single-cycle scan mode: Continuous A/D conversion on one to four channels
 Continuous scan mode: Repetitive A/D conversion on one to four channels
• Four A/D data registers
Four 16-bit A/D data registers (ADDR) are provided. A/D conversion results are stored in A/D
data registers (ADDR) that correspond to the input channels.
• Sample-and-hold function
Sample-and-hold circuits are built into the A/D converter of this LSI, simplifying the
configuration of the external analog input circuitry. Multiple channels can be sampled
simultaneously because sample-and-hold circuits can be dedicated to channels 0 to 2.
 Group A (GrA): Analog input pins selected from channels 0, 1, and 2 can be
simultaneously sampled.
• Offset canceling (OFC) function
The offset canceling processing for the A/D converter is automatically performed.
• Three methods for starting A/D conversion
Software: Setting of the ADST bit in ADCR
Timer: TRGAN, TRG0N, TRG4AN, and TRG4BN from the MTU2
TRGAN, TRG4AN, and TRG4BN from the MTU2S
External trigger: ADTRG (LSI pin)
Rev. 1.00 Jun. 26, 2008 Page 971 of 1692
REJ09B0393-0100