SH7280 Datasheet, PDF (853/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 17 Serial Communication Interface with FIFO (SCIF)
17.3.2 Receive FIFO Data Register (SCFRDR)
SCFRDR is a register that stores serial receive data. The SCIF completes the reception of one byte
of serial data by moving the received data from the receive shift register (SCRSR) into SCFRDR
for storage. Continuous reception is possible until 16 bytes are stored. The CPU can read but not
write to SCFRDR. If data is read when there is no receive data in the SCFRDR, the value is
undefined.
When SCFRDR is full of receive data, subsequent serial data is lost.
SCFRDR is initialized to an undefined value by a power-on reset.
Bit: 7
6
5
4
3
2
1
0
Initial value: -
-
-
-
-
-
-
-
R/W: R
R
R
R
R
R
R
R
17.3.3 Transmit Shift Register (SCTSR)
SCTSR transmits serial data. The SCIF loads transmit data from the transmit FIFO data register
(SCFTDR) into SCTSR, then transmits the data serially from the TXD pin, LSB (bit 0) first. After
transmitting one data byte, the SCIF automatically loads the next transmit data from SCFTDR into
SCTSR and starts transmitting again.
The CPU cannot read or write to SCTSR directly.
Bit: 7
6
5
4
3
2
1
0
Initial value: -
-
-
-
-
-
-
-
R/W: -
-
-
-
-
-
-
-
Rev. 1.00 Jun. 26, 2008 Page 823 of 1692
REJ09B0393-0100