SH7280 Datasheet, PDF (1675/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 31 Electrical Characteristics
31.3.13 IIC3 Module Timing
Table 31.17 I²C Bus Interface 3 Timing
Conditions: V_CC = 3.0 to 5.5 V, AV_CC = AVREF = 4.5 to 5.5V,
V_SS = PLLV_SS = AVREFVSS = AV_SS = 0 V,
Ta = −20°C to +85°C (Consumer specifications),
Ta = −40°C to +85°C (Industrial specifications)
Specifications
Item
Symbol Test Conditions Min.
Typ. Max.
SCL input cycle time
t
SCL
SCL input high pulse width
t
SCLH
SCL input low pulse width
t
SCLL
SCL, SDA input rise time
t
Sr
SCL, SDA input fall time
t
Sf
SCL, SDA input spike pulse
t
SP
removal time*²
12 t + 600
—
pcyc
3 t + 300
—
pcyc
5 t + 300
—
pcyc
—
—
—
—
—
—
—
—
—
300
1t
pcyc
1t
pcyc
SDA input bus free time
t
BUF
Start condition input hold time t
STAH
Retransmit start condition input t_STAS
setup time
5
—
—
3
—
—
3
—
—
Stop condition input setup time t
STOS
Data input setup time
t_SDAS
Data input hold time
t
SDAH
SCL, SDA capacitive load
Cb
3
1 t_pcyc + 20
0
0
—
—
—
—
—
—
—
400
SCL, SDA output fall time*³
t_Sf
20 + 0.1 cb
—
250
Notes: 1. t_pcyc indicates peripheral clock (Pφ) cycle.
2. Depends on the value of NF2CYC.
3. Indicates the I/O buffer characteristic.
Unit Figure
ns Figure 31.54
ns
ns
t *¹
pcyc
ns
ns
t *1
pcyc
t *1
pcyc
t *1
pcyc
t *1
pcyc
ns
ns
pF
ns
Rev. 1.00 Jun. 26, 2008 Page 1645 of 1692
REJ09B0393-0100