SH7280 Datasheet, PDF (505/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
• TIER_5
Bit: 7
6
5
4
3
2
1
0
-
-
-
-
- TGIE5U TGIE5V TGIE5W
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R R/W R/W R/W
Bit
Bit Name
7 to 3 —
2
TGIE5U
1
TGIE5V
0
TGIE5W
Initial
Value
All 0
0
0
0
R/W
R
R/W
R/W
R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
TGR Interrupt Enable 5U
Enables or disables interrupt requests (TGIU_5) by the
CMFU5 bit when this bit in TSR_5 is set to 1.
0: Interrupt requests (TGIU_5) disabled
1: Interrupt requests (TGIU_5) enabled
TGR Interrupt Enable 5V
Enables or disables interrupt requests (TGIV_5) by the
CMFV5 bit when this bit in TSR_5 is set to 1.
0: Interrupt requests (TGIV_5) disabled
1: Interrupt requests (TGIV_5) enabled
TGR Interrupt Enable 5W
Enables or disables interrupt requests (TGIW_5) by the
CMFW5 bit when this bit in TSR_5 is set to 1.
0: Interrupt requests (TGIW_5) disabled
1: Interrupt requests (TGIW_5) enabled
Rev. 1.00 Jun. 26, 2008 Page 475 of 1692
REJ09B0393-0100