SH7280 Datasheet, PDF (720/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 13 Port Output Enable 2 (POE2)
Figure 13.1 shows a block diagram of the POE2.
TIOC3B
TIOC3D
TIOC4A
TIOC4C
TIOC4B
TIOC4D
TIOC3BS
TIOC3DS
TIOC4AS
TIOC4CS
TIOC4BS
TIOC4DS
POE3
POE2
POE1
POE0
Output level comparison
circuit
Output level comparison
circuit
Output level comparison
circuit
Output level comparison
circuit
Output level comparison
circuit
Output level comparison
circuit
Input level detection circuit
Falling edge
detection circuit
Low level
sampling circuit
POECR1,
POECR2
High-impedance
request signal for
MTU2 high-current pins
High-impedance
request signal for
MTU2 channel 0 pins
High-impedance
request signal for
MTU2S high-current pins
Interrupt
request signal
POE7
POE4
POE5
POE6
Input level detection circuit
Falling edge
detection circuit
Low level
sampling circuit
POE8
Input level detection circuit
Falling edge
detection circuit
Low level
sampling circuit
Pφ/8
Pφ/16
Pφ/128
Frequency
divider
SPOER
[Legend]
ICSR1:
ICSR2:
ICSR3:
OCSR1:
OCSR2:
Input level control/status register 1
Input level control/status register 2
Input level control/status register 3
Output level control/status register 1
Output level control/status register 2
Pφ
SPOER: Software port output enable register
POECR1: Port output enable control register 1
POECR2: Port output enable control register 2
Figure 13.1 Block Diagram of POE2
Rev. 1.00 Jun. 26, 2008 Page 690 of 1692
REJ09B0393-0100