SH7280 Datasheet, PDF (922/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 18 Synchronous Serial Communication Unit (SSU)
Initial
Bit
Bit Name Value R/W
Description
3
TEND
0
R/W
Transmit End
[Setting conditions]
• When the last bit of transmit data is transmitted
while the TENDSTS bit in SSCR2 is cleared to 0
and the TDRE bit is set to 1
• After the last bit of transmit data is transmitted while
the TENDSTS bit in SSCR2 is set to 1 and the
TDRE bit is set to 1
[Clearing conditions]
• When writing 0 after reading TEND = 1
• When writing data to SSTDR
2
TDRE
1
R/W
Transmit Data Empty
Indicates whether or not SSTDR contains transmit data.
[Setting conditions]
• When the TE bit in SSER is 0
• When data is transferred from SSTDR to SSTRSR
and SSTDR is ready to be written to.
[Clearing conditions]
• When writing 0 after reading TDRE = 1
• When writing data to SSTDR with TE = 1
• When transmit data is written to SSTDR while the
DMAC is activated by an SSTXI.
• When transmit data is written to SSTDR while the
DISEL bit in MRB of the DTC is 0 if the DMAC/DTC
is activated by an SSTXI interrupt and then DMAC
is activated.
Rev. 1.00 Jun. 26, 2008 Page 892 of 1692
REJ09B0393-0100