SH7280 Datasheet, PDF (103/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 4 Clock Pulse Generator (CPG)
Section 4 Clock Pulse Generator (CPG)
This LSI has a clock pulse generator (CPG) that generates an internal clock (Iφ), a peripheral
clock (Pφ), a bus clock (Bφ), an MTU2S clock (Mφ), and an AD clock (Aφ). The CPG consists of
a crystal oscillator, a PLL circuit, and a divider circuit.
4.1 Features
• Five clocks generated independently
An internal clock (Iφ) for the CPU and cache, a peripheral clock (Pφ) for the peripheral
modules, a bus clock (Bφ = CK) for the external bus interface, an MTU2S clock (Mφ) for the
MTU2S module, and an AD clock (Aφ) for the ADC module can be generated independently.
• Frequency change function
Internal and peripheral clock frequencies can be changed independently using the PLL (phase
locked loop) circuit and divider circuit within the CPG. Frequencies are changed by software
using frequency control register (FRQCR) settings.
• Power-down mode control
The clock can be stopped for sleep mode and software standby mode, and specific modules
can be stopped using the module standby function. For details on clock control in the power-
down modes, see section 28, Power-Down Modes.
Figure 4.1 shows a block diagram of the clock pulse generator.
Rev. 1.00 Jun. 26, 2008 Page 73 of 1692
REJ09B0393-0100