SH7280 Datasheet, PDF (198/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 7 User Break Controller (UBC)
7.3 Register Descriptions
The UBC has the following registers.
Table 7.2 Register Configuration
Channel Register Name
0
Break address register_0
Break address mask register_0
Break bus cycle register_0
1
Break address register_1
Break address mask register_1
Break bus cycle register_1
2
Break address register_2
Break address mask register_2
Break bus cycle register_2
3
Break address register_3
Break address mask register_3
Break bus cycle register_3
Common Break control register
Abbrevia-
tion
R/W
BAR_0
R/W
BAMR_0 R/W
BBR_0
R/W
BAR_1
R/W
BAMR_1 R/W
BBR_1
R/W
BAR_2
R/W
BAMR_2 R/W
BBR_2
R/W
BAR_3
R/W
BAMR_3 R/W
BBR_3
R/W
BRCR
R/W
Initial Value
H'00000000
H'00000000
H'0000
H'00000000
H'00000000
H'0000
H'00000000
H'00000000
H'0000
H'00000000
H'00000000
H'0000
H'00000000
Address
Access
Size
H'FFFC0400 32
H'FFFC0404 32
H'FFFC04A0 16
H'FFFC0410 32
H'FFFC0414 32
H'FFFC04B0 16
H'FFFC0420 32
H'FFFC0424 32
H'FFFC04A4 16
H'FFFC0430 32
H'FFFC0434 32
H'FFFC04B4 16
H'FFFC04C0 32
Rev. 1.00 Jun. 26, 2008 Page 168 of 1692
REJ09B0393-0100