SH7280 Datasheet, PDF (1368/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 25 USB Function Module
25.3.12 USBEP3 Data Register (USBEPDR3)
USBEPDR3 is an 8-byte transmit FIFO buffer for endpoint 3, holding one packet of transmit data
in endpoint 3 interrupt transfer. Transmit data is fixed by writing one packet of data and setting the
EP3PKTE bit in the USB trigger register. When an ACK handshake is received from the host after
one packet of data has been transmitted normally, the EP3TS bit in the USB interrupt flag register
0 is set.
USBEPDR3 can be initialized by means of the EP3CLR bit in USBFCLR.
Bit: 7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Initial value: -
-
-
-
-
-
-
-
R/W: W W W W W W W W
Bit
7 to 0
Bit Name
D7 to D0
Initial
Value
R/W
Undefined W
Description
Data register for endpoint 3 transfer
25.3.13 USBEP0o Receive Data Size Register (USBEPSZ0o)
USBEPSZ0o indicates, in bytes, the amount of data received from the host by endpoint 0o.
USBEPSZ0o can be initialized to H'00 by a power-on reset.
Bit: 7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit
7 to 0
Bit Name

Initial
Value
All 0
R/W Description
R
Number of bytes received by endpoint 0
Rev. 1.00 Jun. 26, 2008 Page 1338 of 1692
REJ09B0393-0100