SH7280 Datasheet, PDF (264/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

Section 8 Data Transfer Controller (DTC)
Table 8.11 DTC Bus Release Timing
Bus Function Extending
Register (BSCEHR)
Setting
Bus Release Timing
(O: Bus must be released;
x: Bus is not released)
DTLOCK DTBST
After
Transfer
After Vector Information
Read
Read
After a
Single data
Transfer
After Write-Back of
Transfer Information
Normal
Transfer
Continuous
Transfer
Setting 1 0
0
×
×
×
O
O
Setting 2* 0
1
×
×
×
O
×
Setting 3 1
0
O
O
O
O
O
Note: * The following restrictions apply to setting 2.
• The clock setting through the frequency control register (FROCR) must be Iφ : Bφ : Pφ =
8 : 4 : 4, 4 : 2 : 2, or 2 : 1 : 1.
• The vector information must be stored in the on-chip ROM or RAM.
• The transfer information must be stored in the on-chip RAM.
• Transfer must be between the on-chip RAM and an on-chip peripheral module or
between the external memory and an on-chip peripheral module.
Rev. 1.00 Jun. 26, 2008 Page 234 of 1692
REJ09B0393-0100