SH7280 Datasheet, PDF(781/1726 Page) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

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SH7280 Datasheet, PDF (781/1726 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

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Section 16 Serial Communication Interface (SCI)

Section 16 Serial Communication Interface (SCI)

This LSI has four channels (SH7286 and SH7285) or two channels (SH7243) of independent

serial communication interface (SCI). The SCI can handle both asynchronous and clock

synchronous serial communication. In asynchronous serial communication mode, serial data

communication can be carried out with standard asynchronous communication chips such as a

Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous Communication

Interface Adapter (ACIA). A function is also provided for serial communication between

processors (multiprocessor communication function).

16.1 Features

â¢ Choice of asynchronous or clock synchronous serial communication mode

â¢ Asynchronous mode:

ï£§ Serial data communication is performed by start-stop in character units. The SCIF can

communicate with a universal asynchronous receiver/transmitter (UART), an asynchronous

communication interface adapter (ACIA), or any other communications chip that employs

a standard asynchronous serial system. There are twelve selectable serial data

communication formats.

ï£§ Data length: 7 or 8 bits

ï£§ Stop bit length: 1 or 2 bits

ï£§ Parity: Even, odd, or none

ï£§ Multiprocessor communications

ï£§ Receive error detection: Parity, overrun, and framing errors

ï£§ Break detection: Break is detected by reading the RXD pin level directly when a framing

error occurs.

â¢ Clock synchronous mode:

ï£§ Serial data communication is synchronized with a clock signal. The SCIF can communicate

with other chips having a clock synchronous communication function.

ï£§ Data length: 8 bits

ï£§ Receive error detection: Overrun errors

â¢ Full duplex communication: The transmitting and receiving sections are independent, so the

SCI can transmit and receive simultaneously. Both sections use double buffering, so high-

speed continuous data transfer is possible in both the transmit and receive directions.

â¢ On-chip baud rate generator with selectable bit rates

â¢ Internal or external transmit/receive clock source: From either baud rate generator (internal

clock) or SCK pin (external clock)

Rev. 1.00 Jun. 26, 2008 Page 751 of 1692

REJ09B0393-0100

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